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The Bloom Filter Optimization Saga: A Deep Dive into Go Assembly and AVX2

Shai Asher

• 16 min read
The Bloom Filter Optimization Saga: A Deep Dive into Go Assembly and AVX2

If you've ever wondered how high-performance Go programs achieve their incredible speeds, the answer often lies hidden just beneath the surface, in files exactly like avx2.s. This file is a fascinating example of targeted, low-level optimization.

So, let's break down what this code does, why it exists, and how it works its magic.

What Does This Code Do? (The High-Level View)

At its core, this file provides a set of highly optimized, hardware-accelerated utility functions for a Go program. It's written in Go assembly language, which is a special syntax that translates directly into machine code for amd64 (x86-64) processors.

The key technology it uses is AVX2 (Advanced Vector Extensions 2), a powerful instruction set that allows the CPU to perform the same operation on large blocks of data simultaneously.

This file provides five key functions:

  1. hasAVX2Support(): This is the "gatekeeper." It checks the CPU at runtime to see if it even supports AVX2. If not, the program will know to use a slower, "pure Go" version of these functions instead.
  2. avx2PopCount(data, length): This function counts the total number of '1' bits (the "population count") in a large slice of data. This is extremely useful in areas like databases, cryptography, and bioinformatics.
  3. avx2VectorOr(dst, src, length): This performs a bitwise OR operation on two large byte slices, storing the result in the dst slice (dst[i] = dst[i] | src[i]).
  4. avx2VectorAnd(dst, src, length): Similar to OR, this performs a bitwise AND operation (dst[i] = dst[i] & src[i]).
  5. avx2VectorClear(data, length): This is a hyper-fast way to set every byte in a large slice to zero.

By processing 32 bytes in a single instruction instead of one at a time in a loop, these functions can provide a massive speedup for data-intensive applications.

A Primer on AVX: The CPU's Superhighway

The star of this code is AVX (Advanced Vector Extensions). To understand why it's so important, think of a normal CPU operation as a single toll booth serving one car at a time. This is a SISD (Single Instruction, Single Data) operation. It's effective, but slow for heavy traffic.

AVX, and its predecessor SSE (Streaming SIMD Extensions), are forms of SIMD (Single Instruction, Multiple Data). This is like building a massive, 16-lane (or 32-lane!) toll plaza. A single instruction (the "toll taker") can now process 16 or 32 "cars" (data elements) in the exact same amount of time it used to take to process one.

This file uses AVX2, which typically operates on 256-bit registers (named YMM0–YMM15). A 256-bit register can hold 32 bytes (32 * 8 bits = 256).

This means an instruction like VPOR (Vectorized Packed OR) can perform a bitwise OR on 32 separate bytes all in a single CPU cycle. This is the source of the incredible performance gains.

A Deeper Look: The Anatomy of a Vectorized Function

Let's look at avx2VectorOr as a perfect example of the pattern used here.

TEXT ·avx2VectorOr(SB), NOSPLIT, $0-24
    MOVQ dst+0(FP), DI       // Load dst pointer
    MOVQ src+8(FP), SI       // Load src pointer
    MOVQ length+16(FP), CX   // Load length in bytes
    ...
    // Check if we have at least 32 bytes
    CMPQ CX, $32
    JL scalar_or_loop        // If not, jump to the slow loop

avx2_or_loop:
    ...
    // Load 32 bytes from src and dst
    VMOVDQU (SI)(DX*1), Y0   // Load 32 bytes from src into YMM0
    VMOVDQU (DI)(DX*1), Y1   // Load 32 bytes from dst into YMM1

    // Perform OR operation
    VPOR Y0, Y1, Y1          // Y1 = Y1 | Y0 (32 bytes at once!)

    // Store result back to dst
    VMOVDQU Y1, (DI)(DX*1)   // Write 32-byte result back to dst
    ...
    JMP avx2_or_loop         // Repeat

scalar_or_loop:
    // This loop processes the remaining 0-31 bytes
    // one byte at a time.
    ...

This code is a classic optimization pattern, often called the "Vector Loop" + "Scalar Tail" pattern:

  1. The "Scalar Tail" Check: It first checks if the data is long enough (32 bytes) to be worth using the AVX2 instructions. If not, it jumps to scalar_or_loop, which processes the "tail" end of the data one byte at a time.
  2. The "Vector Loop": This is the hot path.
    • VMOVDQU: This instruction "Vector Moves" 32 bytes (a "Double Quadword") from memory into the special 256-bit YMM registers (Y0 and Y1).
    • VPOR: This is the magic. In one CPU cycle, it performs a bitwise OR on all 32 bytes in Y0 and Y1.
    • VMOVDQU: It then writes the 32-byte result from Y1 back to memory.
    • The loop repeats, processing 32 bytes every iteration.

avx2VectorAnd and avx2VectorClear follow the exact same pattern, just using VPAND (Vectorized AND) and VPXOR (to zero a register) respectively.

Why this pattern is profound: This design keeps the "hot" vector loop completely free of complex branching. Branching (like if statements) inside a tight loop is a performance killer for modern CPUs, as it can cause "branch mispredictions" that force the CPU to stall. By handling the "messy" end-of-data logic in a completely separate, slower "scalar tail" loop, the main 99% of the work runs on the most optimized, predictable path possible.

Breaking Down the Assembly: The Main Steps

For readers who want a high-level summary, here is the logical flow of a typical function like avx2VectorOr.

  1. Function Prologue & Setup
    • The function is defined and marked as NOSPLIT (a Go runtime optimization).
    • It reads the function arguments (the pointers dst, src, and the length) from the stack frame (FP) and stores them in CPU registers (DI, SI, CX).
  2. The Pre-Loop Check
    • It compares the length to 32.
    • If the length is less than 32, it jumps past the entire vector loop, straight to the "Scalar Tail" section.
  3. The Vector Loop
    • The code calculates the total number of bytes to process in this fast loop (the largest multiple of 32 less than or equal to the length).
    • It enters a loop that does the following:
      • VMOVDQU: Loads 32 bytes from src into a YMM register.
      • VMOVDQU: Loads 32 bytes from dst into another YMM register.
      • VPOR: Performs the 32-byte parallel OR operation.
      • VMOVDQU: Stores the 32-byte result back into dst.
      • ADDQ: Adds 32 to the loop counter.
    • It jumps back to the top of the loop, repeating until all 32-byte chunks are done.
  4. The Scalar Tail
    • This section handles the "leftovers" (the 0-31 bytes at the end).
    • It enters a new, simpler loop that does the following:
      • MOVBQZX: Loads one byte from src.
      • MOVBQZX: Loads one byte from dst.
      • ORQ: Performs the 8-bit OR operation.
      • MOVB: Stores the 1-byte result back into dst.
      • INCQ: Adds 1 to the loop counter.
    • It jumps back to the top of this scalar loop, repeating until the counter equals the total length.
  5. Function Epilogue & Cleanup
    • VZEROUPPER: This critical instruction cleans up the CPU state, preventing performance penalties in other parts of the Go program.
    • RET: The function returns.

A Line-by-Line Breakdown: The Ultimate Deep Dive

For those who want the full story, here is a granular breakdown of the key functions, formatted as commented assembly.

// ### Function 1: The "Gatekeeper" (hasAVX2Support)
// This function is the most important one for safety. It asks the CPU,
// "Do you even support AVX2?"

TEXT ·hasAVX2Support(SB), NOSPLIT, $0-1
    // Defines the Go function `hasAVX2Support`. `NOSPLIT` tells the Go runtime
    // this function is small and doesn't need stack-check code.
    // `$0-1` means 0 bytes of stack frame, 1 byte for the return value (`bool`).

// First check if CPUID supports leaf 7
MOVQ $0, AX
    // Moves the value `0` into the `AX` register. This is setting up a `CPUID`
    // query for "Leaf 0," which asks for basic vendor info and the highest supported leaf.

CPUID
    // Executes the CPU Identification instruction. The CPU populates `AX`, `BX`,
    // `CX`, and `DX` with its response. `AX` will now contain the highest
    // leaf number this CPU supports.

CMPQ AX, $7
    // Compares the result in `AX` (the highest leaf) with the number `7`.
    // We need to ask about "Leaf 7," so we must first check if the CPU
    // even knows what that is.

JL no_avx2
    // "Jump if Less." If the highest leaf is *less than* 7, the CPU is too old
    // to support AVX2. Jump to the `no_avx2` label to return `false`.

// Check for AVX2 support (CPUID.7.0:EBX.AVX2[bit 5])
MOVQ $7, AX
    // Moves the value `7` into `AX`. This is the *real* query: "Tell me about
    // Structured Extended Features" (Leaf 7).

MOVQ $0, CX
    // Moves `0` into `CX`. For Leaf 7, `CX` specifies the "sub-leaf."
    // Sub-leaf 0 contains the AVX2 flag.

CPUID
    // Executes the query. The CPU populates the registers. The `BX` register
    // now contains the feature flags for Leaf 7, Sub-leaf 0.

SHRQ $5, BX
    // "Shift Right Quick." This shifts all the bits in the `BX` register 5
    // positions to the right. The AVX2 flag is at bit 5, so this moves it to bit 0.

ANDQ $1, BX
    // "And Quick." This performs a bitwise `AND` with the value `1`. This
    // zeroes out every bit *except* for bit 0. The `BX` register now
    // contains *only* `1` (if AVX2 is supported) or `0` (if not).

MOVB BX, ret+0(FP)
    // "Move Byte." Moves the final 1-byte result (0 or 1) into the return
    // value slot on the stack (`ret+0(FP)`), which Go will interpret as a `bool`.

RET
    // Returns from the function.

no_avx2:
    // This is the label we jump to if the CPU is too old.

MOVB $0, ret+0(FP)
    // Moves `0` (false) into the return value slot.

RET
    // Returns from the function.

// ### Function 2: The Workhorse (avx2VectorOr)
// This is the canonical example of the Vector/Scalar pattern.

TEXT ·avx2VectorOr(SB), NOSPLIT, $0-24
    // Defines the `avx2VectorOr` function.

MOVQ dst+0(FP), DI
    // Moves the first argument (the `dst` pointer) from the Go frame
    // into the `DI` register.
MOVQ src+8(FP), SI
    // Moves the second argument (the `src` pointer) into the `SI` register.
MOVQ length+16(FP), CX
    // Moves the third argument (the `length`) into the `CX` register.
XORQ DX, DX
    // "Exclusive OR." `XOR`ing a register with itself is the fastest way
    // to set it to `0`. `DX` will be our loop counter/offset, starting at 0.

// Check if we have at least 32 bytes
CMPQ CX, $32
    // Compares the total `length` (`CX`) to `32`.
JL scalar_or_loop
    // "Jump if Less." If `length < 32`, jumps to the scalar tail.

// Calculate aligned length for vector loop
MOVQ CX, R8
    // Copies the `length` (`CX`) into the `R8` register.
SHRQ $5, R8
    // Shifts `R8` right by 5 bits (equivalent to `R8 = R8 / 32`),
    // calculating the *number of chunks*.
SHLQ $5, R8
    // Shifts `R8` left by 5 bits (equivalent to `R8 = R8 * 32`),
    // getting the *total number of bytes* that will be processed by
    // the vector loop (e.g., if length was 100, `R8` is now 96).

avx2_or_loop:
    // Label for the top of the fast vector loop.
CMPQ DX, R8
    // Compares our offset (`DX`) to the vector-loop byte-count (`R8`).
JGE scalar_or_loop
    // "Jump if Greater or Equal." If `offset >= vector_length`, we are
    // done with the vector loop. Jump to the scalar tail.

// Load 32 bytes from src and dst
VMOVDQU (SI)(DX*1), Y0
    // "Vector Move Double Quadword Unaligned." Loads 32 bytes from `src`
    // (address `SI + DX`) into the 256-bit `YMM0` register.
VMOVDQU (DI)(DX*1), Y1
    // Loads 32 bytes from `dst` (address `DI + DX`) into the `YMM1` register.

// Perform OR operation
VPOR Y0, Y1, Y1
    // "Vector Packed OR." Performs a 256-bit (32-byte) parallel `OR`
    // of `YMM0` and `YMM1`, storing the result in `YMM1`.

// Store result back to dst
VMOVDQU Y1, (DI)(DX*1)
    // Stores the 32-byte result from `YMM1` back into `dst` (address `DI + DX`).

ADDQ $32, DX
    // Adds `32` to our offset (`DX`).
JMP avx2_or_loop
    // Jumps to the top of the vector loop.

scalar_or_loop:
    // Label for the top of the slow scalar loop.
CMPQ DX, CX
    // Compares our offset (`DX`) to the *total* `length` (`CX`).
JGE or_done
    // "Jump if Greater or Equal." If `offset >= total_length`, we are
    // completely finished. Jump to the cleanup section.

// Load and process one byte
MOVBQZX (DI)(DX*1), AX
    // "Move Byte with Zero Extend." Loads *one byte* from `dst`
    // (address `DI + DX`) into the `AX` register, zeroing the upper bits.
MOVBQZX (SI)(DX*1), R9
    // Loads *one byte* from `src` (address `SI + DX`) into the `R9` register.
ORQ R9, AX
    // Performs a standard 64-bit `OR` (which works on the bytes in `R9` and `AX`).
MOVB AX, (DI)(DX*1)
    // "Move Byte." Stores the 1-byte result from `AX` back into `dst`.

INCQ DX
    // "Increment Quick." Adds `1` to our offset (`DX`).
JMP scalar_or_loop
    // Jumps to the top of the scalar loop.

or_done:
    // Label for the cleanup.
VZEROUPPER
    // The "Good Citizen" instruction. Clears the upper 128 bits of all
    // `YMM` registers to prevent AVX/SSE transition penalties.
RET
    // Returns from the function.

// ### Function 3: The Hybrid (`avx2PopCount`)
// This is the clever hybrid function that blends AVX2 and SSE.

TEXT ·avx2PopCount(SB), NOSPLIT, $0-24
    // Defines `avx2PopCount`. `$0-24` means 0 bytes of stack, 24 bytes
    // for arguments/return (data unsafe.Pointer, length int, ret int).
MOVQ data+0(FP), SI
    // Load `data` pointer into `SI`.
MOVQ length+8(FP), CX
    // Load `length` into `CX`.
XORQ AX, AX
    // Zero out `AX`, which will be our total `popcount` accumulator.
XORQ DX, DX
    // Zero out `DX`, our loop counter/offset.

CMPQ CX, $32
    // Compare `length` to 32.
JL scalar_loop
    // If `length < 32`, jump to the scalar tail.

// Prepare for AVX2 processing
MOVQ CX, R8
    // Copy `length` to `R8`.
SUBQ DX, R8
    // `R8` = `R8` - `DX` (DX is 0, so R8=length). `R8` is remaining bytes.
SHRQ $5, R8
    // `R8 = R8 / 32` (number of 32-byte chunks).
SHLQ $5, R8
    // `R8 = R8 * 32` (aligned length for AVX2 loop).

avx2_loop:
    // Label for the fast vector loop.
CMPQ DX, R8
    // Compare offset `DX` to aligned length `R8`.
JGE scalar_loop
    // If `DX >= R8`, jump to scalar tail.

// Load 32 bytes (256 bits) using AVX2
VMOVDQU (SI)(DX*1), Y0
    // Load 32 bytes from `data` (address `SI + DX`) into `YMM0`.

// Count bits using a simpler method: process as uint64s using POPCNT
// Extract and process each 64-bit chunk
VMOVQ X0, R9
    // "Vector Move Quadword." Moves the lowest 64 bits from `YMM0`
    // (which is `XMM0`) into the 64-bit register `R9`.
POPCNTQ R9, R9
    // "Population Count." Counts the `1` bits in `R9` and stores the total in `R9`.
ADDQ R9, AX
    // Add this chunk's count to the total accumulator `AX`.

VPEXTRQ $1, X0, R9
    // "Vector Packed Extract Quadword." Extracts the *second* 64-bit chunk
    // (index 1) from `XMM0` (the lower 128 bits of `YMM0`) into `R9`.
POPCNTQ R9, R9
    // Count the bits in this chunk.
ADDQ R9, AX
    // Add to the total.

VEXTRACTI128 $1, Y0, X1
    // "Vector Extract 128-bit." Extracts the *upper* 128-bit lane (index 1)
    // from `YMM0` into `XMM1`.
VMOVQ X1, R9
    // Move the lowest 64 bits of `XMM1` (the third chunk) into `R9`.
POPCNTQ R9, R9
    // Count the bits.
ADDQ R9, AX
    // Add to the total.

VPEXTRQ $1, X1, R9
    // Extract the *second* 64-bit chunk (index 1) from `XMM1`
    // (the fourth chunk) into `R9`.
POPCNTQ R9, R9
    // Count the bits.
ADDQ R9, AX
    // Add to the total.

ADDQ $32, DX
    // Advance our offset by 32 bytes.
JMP avx2_loop
    // Repeat the vector loop.

scalar_loop:
    // Label for the scalar tail.
CMPQ DX, CX
    // Compare offset `DX` to the total `length` `CX`.
JGE done
    // If `DX >= CX`, we're finished.

MOVBQZX (SI)(DX*1), R9
    // "Move Byte with Zero Extend." Load *one byte* from `data`
    // (address `SI + DX`) into `R9`.
POPCNTQ R9, R9
    // Count the bits in that single byte.
ADDQ R9, AX
    // Add to the total.

INCQ DX
    // Increment offset by 1.
JMP scalar_loop
    // Repeat the scalar loop.

done:
    // Label for cleanup.
VZEROUPPER
    // "Good Citizen" cleanup.
MOVQ AX, ret+16(FP)
    // Move the final total from `AX` into the return slot on the stack.
RET
    // Return from function.

// ### Function 4 & 5: (avx2VectorAnd & avx2VectorClear)
// These functions are nearly identical to `avx2VectorOr`.

// `avx2VectorAnd` is the same, but replaces `VPOR Y0, Y1, Y1` with:
VPAND Y0, Y1, Y1
    // "Vector Packed AND." Performs a 256-bit parallel `AND`.
// ...and it replaces the scalar `ORQ` with `ANDQ`.

// `avx2VectorClear` is even simpler. It zeros a register *before* the loop:
VPXOR Y0, Y0, Y0
    // `XOR` a register with itself to zero it out.
// And then *inside* the loop, it just stores the zeros:
VMOVDQU Y0, (DI)(DX*1)
    // Stores 32 bytes of zeros.
// The scalar loop just stores single zero bytes (`MOVB $0, (DI)(DX*1)`).

The Nuts & Bolts: Inside the "Vector Loop" Workhorse

While the "Scalar Tail" is important for correctness, the "Vector Loop" is the engine that provides the speed. Let's look at its key components:

  • VMOVDQU (Vector Move Double Quadword Unaligned): This is the workhorse for data loading and storing.
    • V = Vector (part of the AVX instruction set)
    • MOV = Move
    • DQU = Double Quadword (256 bits or 32 bytes)
    • U = Unaligned. This is the most critical part. It means the data (from the Go slice) does not have to start on a perfect 32-byte memory boundary. An aligned move (VMOVDQA) is slightly faster but will crash the program if the data is misaligned. VMOVDQU is the robust and flexible choice that makes this operation safe for general-purpose Go slices.
  • VPOR / VPAND (Vectorized Packed OR/AND): This is the core of SIMD.
    • V = Vector
    • P = Packed. This means the instruction operates on all the packed data elements within the register (i.e., all 32 bytes).
    • In a single CPU cycle, VPOR Y0, Y1, Y1 it performs 32 separate OR operations in parallel. This is the source of the 32x potential speedup.
  • The Loop Structure (JMP avx2_or_loop): The loop itself is "dumb" by design. It just increments an offset (DX) by 32 and jumps back to the top. As we'll see next, this simplicity enables the CPU's branch predictor to work perfectly, ensuring the pipeline never stalls.

The Nuts & Bolts: The "Scalar Tail" Pattern (Why Two Loops Are Faster Than One)

The core problem is that real-world data is messy. You might have 100 bytes to process. The vector loop can handle 3 * 32 = 96 bytes, but that leaves 4 bytes "left over" (the "tail").

A naive solution would be one "smart" loop with an if statement:

// Naive (Bad) Solution
while (bytes_left > 0) {
    if (bytes_left >= 32) {
        // Do fast 32-byte AVX2 operation
    } else {
        // Do slow 1-byte scalar operation
    }
}

This looks efficient, but that if inside the hot loop is a performance disaster. It causes Branch Misprediction.

Modern CPUs use a "pipeline"—they start executing the next 10-20 instructions before the current one finishes. When the pipeline hits an if (a "branch"), The CPU must guess which path will be taken.

  • If it guesses right: The pipeline stays full, and everything runs at maximum speed.
  • If it guesses wrong (a Misprediction): It's a catastrophe. The CPU must flush its entire pipeline—throw away all the work it was speculatively doing—and restart from the correct path. This is a massive stall.

In the naive loop, the CPU will guess if (bytes_left >= 32) is true for the first few iterations. But on the last iteration, the condition suddenly becomes false, causing a misprediction and a stall right inside the critical loop.

The "Scalar Tail" pattern solves this by splitting the work into two "dumb" loops:

  1. The Vector Loop: This loop only processes the 32-byte chunks. Its branch condition is simple and 100% predictable. It runs at full speed with zero mispredictions.
  2. The Scalar Loop: After the fast loop is done, this separate, simple loop handles the 4 leftover bytes. It's slower per byte, but it only runs a few times.

This pattern allows the "fast path" (99% of the work) to be perfectly predictable by handling the "messy" data in a separate "slow path."

The Curious Case of avx2PopCount

The avx2PopCount function is particularly clever. Instead of a complex, purely-AVX2 bit-counting algorithm (which is very difficult to write), it uses a hybrid approach:

  1. It uses VMOVDQU to load 32 bytes into a YMM register (fast).
  2. It then uses a series of extraction instructions (VMOVQ, VPEXTRQ, VEXTRACTI128) to break that 256-bit register into four 64-bit chunks.
  3. It feeds each 64-bit chunk to the scalar POPCNTQ instruction, which is also hardware-accelerated (part of the SSE4.2 set) and counts the bits in a 64-bit integer very quickly.

This approach gets the best of both worlds: the massive data-loading speed of AVX2 combined with the simplicity and speed of the dedicated POPCNTQ instruction.

Why this strategy is profound: The author recognized that the true bottleneck is often memory access, not the computation itself. They used AVX2 to solve the memory bottleneck (loading 32 bytes at once) and then used the most specialized instruction (POPCNTQ) for the actual counting. This "best of both worlds" strategy is often faster and far simpler to implement than a "pure" AVX2 solution.

Why This "Best of Both Worlds" Is So Effective

That claim that the hybrid model is "faster and simpler" is key. Let's break down why it's true:

  • Simplicity: A "pure" AVX2 bit-counting algorithm is notoriously complex. It often requires a "bitsliced" approach, using multiple vector-shuffle (VPSHUFB) and parallel-add (VPADDD) instructions to simulate a population count across all 32 bytes at once. This is difficult to write and maintain. The hybrid approach, by contrast, is simple: load 32 bytes, break them into 8-byte chunks, and use the POPCNTQ instruction that's already perfectly optimized for this exact job.
  • Speed: While a hypothetical, perfectly-tuned pure AVX2 popcount might be faster, this hybrid approach is often just as fast or faster in practice. The POPCNTQ instruction is implemented in dedicated, blazing-fast hardware (often 1-3 clock cycles). The main performance bottleneck is almost always loading data from memory, which VMOVDQU solves. By offloading the actual counting to the POPCNTQ unit, the code ensures the computation is never the bottleneck; the CPU is just feeding its specialized counting unit as fast as AVX2 can load the data.

The Unconventional and the Profound: A Closer Look

Beyond the high-level patterns, the specific instructions used in this file are a masterclass in hardware-level programming.

CPUID: The "CPU, Tell Me About Yourself" Instruction

Found in ·hasAVX2Support, CPUID (CPU Identification) is not for computing data; it's for querying the CPU's identity and features.

The code "asks a question" by putting 7 in the AX register and 0 in CX. The CPUID instruction then "answers" by populating other registers with feature flags. The code checks bit 5 of the BX register—the specific flag designated by Intel/AMD to mean "AVX2 is available."

This is the most "meta" instruction in the file. It's essential for defensive programming at the hardware level, allowing the program to adapt at runtime and avoid crashing with an "Illegal Instruction" error on older CPUs.

VZEROUPPER: The "Good Citizen" Cleanup Instruction

You see this at the end of every AVX2 function. It seems to do nothing, but it's critical for performance in a mixed-code environment like Go.

  • The Problem: 256-bit AVX registers (YMM) share their lower 128 bits with older 128-bit SSE registers (XMM). When this code uses a YMM register, it leaves data in the "upper 128 bits."
  • The Penalty: If this "dirty" state is left behind, the CPU has to pause and save/restore it every time it switches between AVX code and the Go runtime's older SSE code. This is extremely slow.
  • The Solution: VZEROUPPER is a cleanup instruction. It zeros out the upper 128 bits, telling the CPU, "I'm done with 256-bit mode." This prevents the performance penalty, making the function a "good CPU citizen" that doesn't slow down other parts of the program.

VEXTRACTI128: The "Vector Lane Switcher"

This instruction, used in avx2PopCount, highlights the complex internal structure of AVX registers. A 256-bit YMM register is treated as two 128-bit "lanes."

The instruction VEXTRACTI128 $1, Y0, X1 means: "Take the upper 128-bit lane (lane 1) from the YMM0 register and copy it into the XMM1 register."

This is the "bridge" instruction that allows the hybrid avx2PopCount function to work. It pulls data out of the 256-bit vector world so it can be fed to the 64-bit scalar POPCNTQ instruction.

POPCNTQ: The "One-Job Wonder"

Also in avx2PopCount, POPCNTQ (Population Count) is the ultimate specialty tool. It does one job: it counts the total number of 1 bits in a 64-bit register and returns the integer total.

Without this, the code would need a complex loop of shifts and additions. POPCNTQ does it all in a single, lightning-fast hardware operation.

Conclusion

This single assembly file is a an example of high-performance computing. It shows how Go programs can "drop down" to the metal when absolute speed is required, using advanced CPU features like AVX2 to process huge amounts of data in the blink of an eye. It's a perfect blend of high-level Go logic (the "pure Go" fallback) and low-level, high-impact assembly optimization.

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